Design-for-Test (DFT) and BIST Engineer

About the role

Working on next-generation RF and Bluetooth/Wireless LAN chipsets.

Requirements

• 5+ years of relevant industrial DFT experience
• Strong problem-solving and debugging skills
• Ability to work independently
• Memory BIST – Siemens Tessent
• Gate-level simulation and debug
• Scan compression – SEQ / Ultra / TestKompress
• ATPG – TetraMAX
• ATPG diagnosis, ATE debug, and silicon bring-up
• DFT pattern translation – VTRAN
• RTL design – Verilog/SystemVerilog
• STA and timing analysis – PrimeTime
• Automation/scripting – Tcl, Perl, and/or Python
• CDC, clock gating checks, and timing constraints

Schedule

• Onsite, 5 days/week
• 6+month contract

How to apply

• Submit your resume in a Word document (.doc/.docx) with the month and year clearly listed for each previous position.
• Email your resume and use “611014-Design For Test Engineer” as the email subject line.

Location

• San Diego/ San Jose, CA