Hardware Design and Failure Analysis Engineer

We are Hiring for Hardware Design and Failure Analysis Engineer - San Jose, CA - Onsite - 6+ Months Contract role.
Hardware Design and Failure Analysis Engineer
San Jose, CA - Onsite
6+ Months Contract
Skills:
EIS: ASIC Ciruit Design - Analog and Mixed Signal IC Circuit design~EIS: Thermal Analysis~EIS: Embedded Digital Hardware Design and Development
Hardware Design and Failure Analysis Engineer
Education & Experience: B.S. or M.S. in Electrical Engineering, Computer Engineering, Materials Science, or related field with 10+ years of progressive experience in hardware engineering, board design, or system-level failure analysis.
High-Speed Hardware Expertise: Well versed in modern system architectures (PCIe Gen4/5/6, DDR4/5, HBM, 56G/112G/224G SerDes, optical transceivers).
Power & Signal Integrity: Proven ability to debug complex power distribution network issues/multi-phase VRM transient droop, PMBus/SVID telemetry, switching noise) and high-speed signal integrity anomalies.
Supplier Engagement: Hands-on experience directing external silicon suppliers and analytical Laboratories through component-level physical FA.
Communication: Strong executive presence with proven capability to articulate complex technical findings to cross-functional leaders and enterprise customers.
Preferred Qualifications
Experience leading hardware quality or reliability taskforces for hyperscale cloud service providers (e.g., Microsoft, Meta, Google, AWS).
Knowledge of advanced packaging technologies (chiplets, 2.5D/3D ICs, CoWoS) and silicon failure mechanisms.
Proficiency in writing custom Python or C automation tools to recreate corner-case/intermittent hardware race conditions.
Skills: EIS: ASIC Ciruit Design - Analog and Mixed Signal IC Circuit design~EIS: Thermal Analysis~EIS: Embedded Digital Hardware Design and Development
Experience Required: 6-8 Years
Interested! Please share your updated resume