IP Design Verification Engineer

Tasks

• Develop and maintain UVM-based verification environments for IP-level designs.
• Implement UVM components, including drivers, monitors, sequencers, agents, scoreboards, and test environments.
• Develop constrained-random test scenarios using SystemVerilog.
• Create and execute verification test plans and test cases.
• Implement assertions and functional coverage to ensure design quality.
• Debug simulation failures, analyze issues, and drive regression closure.
• Perform protocol-level verification of the assigned IP.
• Collaborate with RTL design and verification teams to resolve functional issues.

Requirements

• Strong hands-on experience in SystemVerilog and UVM.
• Experience with RTL-level IP functional verification.
• Expertise in UVM testbench development and component integration.
• Strong knowledge of constrained-random stimulus generation.
• Experience with SystemVerilog Assertions (SVA) and functional coverage.
• Hands-on experience with simulation debugging and regression management.
• Ability to develop test plans and drive functional coverage closure.
• Strong understanding of protocol-level verification for the relevant IP.

Schedule

• 6-Month Contract

How to apply

• DM me directly on LinkedIn or share.

Location

• Dallas, TX