Physical Design Engineer

🚨 Hiring: Senior Physical Design Engineer📍 Location: Sunnyvale, CA🏢 Work Mode: Hybrid
💼 Experience: 5–10 YearsWe are looking for a Senior Physical Design Engineer with strong experience in RTL-to-GDSII implementation for low-power SoCs on advanced nodes.🔹 Key Responsibilities• Drive physical design flow from synthesis to GDSII• Floorplanning, placement, CTS, routing, and timing closure• Deliver low-power designs using advanced UPF methodologies• Work on 5nm / 3nm advanced nodes• Resolve SoC/Subsystem integration challenges• Handle SDC constraints and UPF promotion/pushdown• Develop automation flows using Tcl, Python, and Shell• Collaborate on design closure and signoff• Mentor junior team members• Contribute to flow and methodology improvements🔹 Required Skills• Synopsys Fusion Compiler• Physical Design / RTL-to-GDSII• Low Power Design / UPF• PPA Optimization• 5nm / 3nm• Tcl / Python / Shell• SoC hierarchy and integration• Signoff flows and constraint management🔹 Preferred• Top-level SoC integration• PrimeTime / ICV• DFM checks🎓 Education: B.Tech/M.Tech in ECE, EE, VLSI or related field📩 Interested candidates? DM me your updated resume.#Hiring #PhysicalDesign #PD #VLSI #ASIC #Semiconductor #PhysicalDesignEngineer #FusionCompiler #UPF #GDSII #RTL #PPA #SoC #TimingClosure #Sunnyvale #USJobs #USCitizen #GreenCard