Physical Design Engineer

Requirements

• experienced Physical Design Engineers with hands-on expertise in RTL-to-GDSII implementation and ASIC backend design.
• RTL-to-GDSII implementation
• Logic Synthesis, Place & Route (P&R)
• Static Timing Analysis (STA) and Timing Closure
• Synopsys ICC2 and Fusion Compiler
• Synopsys PrimeTime
• Calibre – Physical Verification (DRC/LVS)
• Clock Tree Synthesis (CTS) and Clock Gating
• Floorplanning, Buffer/Repeater Insertion
• Scan Stitching and PPA Optimization
• Verilog/SystemVerilog

How to apply

• Share your updated resume by email.

Location

• San Diego, CA
• Santa Clara, CA
• Austin, TX
• Chandler, AZ