Physical Design Engineer

About the role

Tek Navigators is looking for an experienced Physical Design Engineer to join an exciting opportunity in semiconductor and chip design.

Tasks

• Own full-chip, top-level floorplanning, including die/partition planning and macro/memory placement.
• Handle partition abutment, pin/port alignment, repeating structures, and channel/feedthrough planning.
• Drive top-level PPA optimization (Power, Performance, and Area).
• Plan and review power grids / PDN in coordination with EM/IR sign-off.
• Develop and maintain top-level SDC constraints and timing budgets.
• Collaborate with ASIC vendors, IP partners, and block-level physical design teams.

Requirements

• Experienced
• Cadence Innovus
• Synopsys Fusion Compiler
• Full-Chip / Top-Level Floorplanning
• PPA Optimization
• Power Grid / PDN Planning
• SDC, STA & Timing Closure
• Independent Candidates Only

How to apply

• Share your updated resume and availability to connect.

Location

• Austin, TX / San Jose, CA (Hybrid)