Senior ASIC/SoC RTL Design Engineer

About the role

Support an ASIC/SoC RTL reverse engineering project in San Diego, California.

Tasks

• Analyze and understand existing ASIC/SoC RTL implementations, design structures, and digital logic.
• Perform RTL analysis to identify module functionality, design intent, and architectural behavior.
• Trace control and data paths across complex RTL hierarchies.
• Analyze FSMs, registers, interfaces, and logic dependencies.
• Document design behavior, architectural findings, and RTL dependencies.
• Support design reconstruction, functional interpretation, or equivalent RTL implementation where required by the project.
• Collaborate with design, verification, and architecture teams to resolve technical questions.
• Review design functionality using simulation, waveform analysis, and relevant RTL analysis tools.
• Identify design issues, ambiguities, and functional discrepancies during the analysis process.
• Maintain clear technical documentation throughout the project.

Requirements

• 10+ years of experience in ASIC/SoC RTL design or a closely related digital design discipline.
• Strong hands-on experience with Verilog and SystemVerilog RTL.
• In-depth understanding of digital logic design, RTL coding, and microarchitecture.
• Experience analyzing complex RTL codebases and understanding existing design behavior.
• Strong knowledge of FSMs, datapaths, control logic, registers, and digital interfaces.
• Must be willing to relocate temporarily to San Diego.

Schedule

• Onsite
• For 3 Months
• Approximately 2–3 months

Location

• San Diego, CA