Senior ASIC/SoC RTL Design Engineer

About the role

Support an RTL Reverse Engineering and Design Analysis project in San Diego, California.

Tasks

• Analyze existing ASIC/SoC designs, trace control and data paths, understand microarchitecture, and document design functionality.

Requirements

• 10+ years of experience in ASIC/SoC RTL Design or Digital Design Engineering.
• Strong hands-on expertise in Verilog and SystemVerilog.
• Deep understanding of RTL coding, digital logic design, and microarchitecture.
• Strong experience analyzing and understanding complex existing RTL codebases.
• Excellent knowledge of FSMs, datapaths, registers, control logic, and digital interfaces.
• Experience with RTL simulation, debugging, and waveform analysis.
• Ability to understand complex hardware functionality and reverse engineer existing RTL designs.
• Strong analytical, problem-solving, and technical documentation skills.
• US Citizens and Green Card Holders Only

Schedule

• Temporary
• Onsite (Temporary Relocation Required)

How to apply

• Send your updated resume by email.

Location

• San Diego, CA