Verification Engineer Job in Melbourne, FL | Arvind

Join Arvind as a Verification Engineer in Melbourne, Florida and contribute to cutting-edge FPGA verification and hardware validation processes. We seek a skilled engineer to design and implement verification environments using SystemVerilog and UVM methodology. Key Responsibilities Design and develop verification environments with SystemVerilog to support FPGA verification efforts. Perform lab testing to validate interactive hardware and software functionality. Apply Universal Verification Methodology (UVM) for creating testbenches and verification components. Collaborate with cross-functional teams to ensure comprehensive design verification. Analyze verification outcomes and provide detailed reports with recommendations for improvements. Maintain accurate documentation of verification procedures and results. Engage in project planning and development lifecycle activities to meet deadlines. Required and Preferred Qualifications Bachelor's degree in a STEM discipline. Expert proficiency in SystemVerilog and FPGA verification techniques. Hands-on experience with UVM methodology. Proven experience in lab testing and hardware/software verification processes. Successful candidates will thrive in a collaborative, quality-focused technical environment. Familiarity with industry-standard verification tools is a plus. This role requires effective communication with technical and managerial teams to align on project objectives. Reporting to the Engineering Manager, you will work closely with hardware and software teams to ensure seamless product integration and functionality. If you are passionate about verification engineering and eager to drive innovative solutions, we encourage you to apply for this full-time position based in Melbourne, FL.