Verification Engineer – FPGA & SystemVerilog | Melbourne, FL

Arvind is hiring a full-time Verification Engineer in Melbourne, Florida. In this on-site role, you will help ensure the reliability and performance of FPGA designs through SystemVerilog development, UVM-based verification, and hands-on lab testing.

Key Responsibilities

• Design and implement SystemVerilog verification environments for FPGA designs.
• Develop testbenches and checking mechanisms using Universal Verification Methodology (UVM).
• Conduct lab testing to validate hardware and software interactions.
• Collaborate with hardware, software, and other cross-functional teams to strengthen design verification.
• Analyze verification results, report findings to stakeholders, and recommend improvements.
• Document verification procedures, test results, and relevant findings.
• Participate in project planning and the product development lifecycle to support timely delivery.

Required Qualifications

• Bachelor’s degree in a STEM field.
• Expert-level proficiency in SystemVerilog and FPGA verification.
• Experience with UVM methodology.
• Relevant experience in lab testing and verification processes.

Role Details

• Employer: Arvind
• Location: Melbourne, Florida, United States
• Work arrangement: On-site; not remote eligible
• Employment: Full-time
• Salary: $110,000 per year
• Reports to: Engineering Manager

Successful candidates bring a collaborative approach and a strong commitment to quality. Familiarity with industry-standard verification tools is beneficial. Apply to contribute your verification engineering expertise to product development at Arvind.