Verification Engineer in Melbourne, Florida - Arvind

Arvind is seeking a skilled Verification Engineer to join our engineering team in Melbourne, Florida. This full-time role is essential for ensuring the reliability and performance of our verification processes.

Key Responsibilities

• Design and implement verification environments using SystemVerilog to support FPGA verification.
• Conduct lab testing to validate hardware and software interaction.
• Utilize Universal Verification Methodology (UVM) for developing testbenches and verification mechanisms.
• Collaborate with cross-functional teams to ensure robust design verification processes.
• Analyze verification results and report findings to stakeholders, recommending improvements.
• Maintain thorough documentation of verification procedures and results.
• Participate in project planning and development lifecycle to ensure timely deliverables.

Required and Preferred Qualifications

• Bachelor's degree in a STEM field.
• Expert-level proficiency in SystemVerilog and FPGA verification.
• Experience with UVM methodology.
• Relevant experience in lab testing and verification processes.

Successful candidates will thrive in a collaborative technical environment focused on quality. Familiarity with industry-standard verification tools is beneficial.

This position requires effective communication with technical and managerial teams to align on project goals. The Verification Engineer will report to the Engineering Manager and work closely with hardware and software teams to ensure seamless product integration and functionality.

If you are passionate about verification engineering and eager to contribute innovative solutions in the tech industry, we encourage you to apply.