ASIC/RTL Design Engineer 5

Tasks

• Build behavioral models of analog and mixed-signal circuits (PLLs, clocking, ADC/DAC, TX/RX analog front ends, calibration loops) in SystemVerilog.
• Those models drop into a SystemVerilog UVM verification environment used for high-speed SerDes and SoC IP.
• Work closely with analog circuit designers, RTL designers and verification engineers.
• Lead and participate in the modeling and verification of leading-edge designs in advanced CMOS processes.
• Read schematics, netlists and circuit specifications to define what each model must capture.
• Develop model architecture and accuracy targets, balancing fidelity against simulation speed.
• Write behavioral SystemVerilog models of analog blocks.
• Validate models against transistor-level simulation results.
• Debug simulation failures and find the root cause in the model, RTL or testbench.
• Document model behavior, limitations and interfaces.

Requirements

• Hands-on experience writing behavioral models of analog circuits in SystemVerilog.
• Working knowledge of analog and mixed-signal circuit fundamentals and of the SystemVerilog UVM methodology, with proven skill debugging failures in simulation and waveforms.
• Familiarity with high-speed interface standards is a plus.
• RTL coding experience and Analog Design/Modeling experience.

Location

• San Jose, CA (Onsite)