ASIC/RTL Design Engineer 5

🚨 We’re Hiring | ASIC/RTL Design Engineer 5 | San Jose, CA 🚨
We are looking for an experienced ASIC/RTL Design Engineer with strong expertise in RTL coding, Analog/Mixed-Signal Design, and SystemVerilog behavioral modeling to support advanced semiconductor, high-speed SerDes, and SoC IP development initiatives.
📌 Position: ASIC/RTL Design Engineer 5
📍 Location: San Jose, CA
🏢 Work Mode: Day 1 Onsite
Apply Now: Please share your updated resume
🔑 Key Requirements:
• Hands-on experience developing behavioral models of analog circuits using SystemVerilog.
• Strong RTL coding and SystemVerilog development experience.
• Experience modeling PLLs, clocking circuits, ADC/DAC, TX/RX analog front ends, and calibration loops.
• Working knowledge of Analog and Mixed-Signal circuit fundamentals.
• Experience integrating behavioral models into SystemVerilog UVM verification environments.
• Ability to read and interpret schematics, netlists, and circuit specifications.
• Experience validating behavioral models against transistor-level simulation results.
• Strong debugging skills using simulation logs and waveforms.
• Experience identifying root causes across behavioral models, RTL, and testbenches.
• Hands-on experience with Synopsys VCS, LTspice, and HSPICE simulation tools.
• Ability to collaborate with Analog Designers, RTL Designers, and Verification Engineers.
• Experience with high-speed SerDes interfaces and SoC IP is a plus.
➕ Good to Have:
• Experience with advanced CMOS process designs.
• Knowledge of high-speed interface standards.
• Experience balancing behavioral model accuracy and simulation performance.
• Strong documentation skills for model behavior, limitations, and interfaces.
📢 Interested candidates: Please share your updated resume, current location, work authorization, total experience, relevant experience, expected rate, and contact details.
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