ATE Test Engineer

About the role

Support digital, PMIC, RF, and mixed-signal test programs using Teradyne J750 ATE platforms.

Collaborate with design engineering teams on first-silicon bring-up, device characterisation, test program development, and production release.

Tasks

• Develop and debug test programs for digital, PMIC, RF, and mixed-signal products using Teradyne J750 ATE and bench setups.
• Support first-silicon debugging, device characterisation, test program bring-up, and production release.
• Debug digital vectors, including JTAG, SCAN, ATPG, Functional, and MBIST.
• Perform device characterisation across PVT (Process, Voltage, and Temperature).
• Characterise RF, PMIC, and mixed-signal IPs, including ADC, DAC, and PLL.
• Drive yield improvement, test time reduction, and production test optimisation.
• Collaborate with Product, Design, Quality, and Foundry Engineering teams.

Requirements

• Degree in Electronics or Electrical Engineering.
• 2–7 years of relevant test engineering experience preferred.
• Hands-on experience with Teradyne J750 ATE is mandatory.
• Experience with bench instrumentation for IC characterisation.
• Strong understanding of analogue and digital electronics.
• Excellent analytical, debugging, and problem-solving skills.
• Strong communication skills and ability to work independently.
• 8+ Years

Schedule

• 100% Onsite

How to apply

• Send your updated resume by email.
• Mention “ATE Test Engineer – J750” in your application.

Location

• San Jose, CA
• Dallas, TX
• Redmond, WA
• Tucson, AZ