CPU Verification Engineer RISC-V

About the role

Qualcomm is seeking a Design Verification Engineer to work with Chip Architects to validate CPU and SOC-level micro-architecture concepts. The role focuses on a selected part of CPU design verification, ensuring it meets the standards for launch readiness in the end product.

Responsibilities

• Work with CPU and SOC Architects to understand concepts and high-level system requirements.
• Develop detailed test and coverage plans based on architecture and micro-architecture.
• Develop verification methodology for scalability and portability across environments.
• Develop verification environments, including stimulus, checkers, assertions, trackers, and coverage.
• Develop verification plans and testbenches for the functional domain.
• Execute verification plans, including design and DV environment bring-up, regressions, feature enablement, and debugging test failures.
• Track and report DV progress using metrics, including bugs and coverage.

Requirements

• Extensive knowledge of industry instruction set architectures, particularly RISC-V.
• Deep knowledge of microprocessor verification functions and architectures, including cache coherence, memory ordering and consistency, prefetching, branch prediction, renaming, speculative execution, and address translation and memory management.
• Knowledge of Random Instruction Sequencing (RIS) and testing designs at block/unit and subsystem/chip levels to prove correctness.
• Experience leading a small team of verification engineers performing CPU verification.
• Advanced techniques such as formal verification, assertions, and silicon bring-up are helpful.
• In-depth knowledge of microprocessor functions, architectures, and micro-architectures.
• Experience writing test plans and portable testbenches.

Key facts

• The role focuses on CPU design verification and validating CPU and SOC micro-architecture concepts.
• Extensive knowledge of instruction set architectures, particularly RISC-V, is preferred.
• The work includes verification plans, testbenches, regressions, and debugging.