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Design For Test (DFT) Engineer
External job listingat Protingent
About the role Work on next-generation RF and Bluetooth/Wireless LAN chipsets. Requirements 5+ years of DFT experience Siemens Tessent / Memory BIST ATPG / Tetramax Scan Compression Gate-...
External source - not verified3 weeks agoOpen until: Jan 10, 2027
Salary
Not provided
Location
San Jose, United States
Employment type
Full time
Workplace
Not provided
Design For Test (DFT) Engineer
San Jose, United States
Job description
About the role
Work on next-generation RF and Bluetooth/Wireless LAN chipsets.
Requirements
- 5+ years of DFT experience
- Siemens Tessent / Memory BIST
- ATPG / Tetramax
- Scan Compression
- Gate-level simulation amp; debug
- ATE debug amp; silicon bring-up
- Tcl / Perl / Python
- Verilog / SystemVerilog
- STA / PrimeTime knowledge
Schedule
- Contract: 6 months
- Onsite
- W2 only
Pay
- $100-$130/hr on W2
How to apply
- Send your resume directly by email or DM.
Location
- San Jose, CA