Design Verification Engineer

About the role

We are seeking an experienced Design Verification Engineer to join the Interface IP Design Verification team.

Tasks

• Own verification of IP subsystems such as PCIe, Ethernet, CPU (ARM/ARC), low-power peripherals, and sensors.
• Develop and maintain SystemVerilog/UVM-based verification environments.
• Understand vendor IP configurations and coordinate with internal IP teams.
• Collaborate with integration and SoC Design Verification teams.
• Drive coverage closure, analyze verification gaps, and ensure sign-off.
• Validate functionality, performance, and corner-case scenarios.

Requirements

• 8+ years of Design Verification experience.
• Strong hands-on experience with SystemVerilog and UVM.
• Knowledge of interfaces and protocols such as PCIe, Ethernet, AXI/AMBA, and ARM/ARC CPUs.
• Experience building scalable and reusable testbenches.
• Strong debugging, problem-solving, and communication skills.
• Ability to work independently in a fast-paced environment.
• Preferred: Experience with vendor IP/VIP handling and integration.
• Preferred: Strong understanding of IP verification and SoC integration.

Schedule

• Onsite

How to apply

• Share your updated resume by email.

Location

• Bay Area (San Jose, CA)