Design Verification Engineer

Tasks

• Developing functional verification environments using SystemVerilog and UVM
• Building monitors, checkers, scoreboards, and assertions
• Verifying AMBA bus protocols and ARM CPU architectures
• Working with constrained-random stimulus and functional coverage
• Automating verification workflows using Python, Perl, Shell, and Makefile
• Debugging complex issues and collaborating with cross-functional engineering teams

Requirements

• Strong hands-on experience with SystemVerilog & UVM
• Solid understanding of AMBA bus protocols and ARM CPUs
• Experience with functional verification methodologies and coverage-driven verification
• Familiarity with Unix, configuration management, bug-tracking, and verification dashboard tools
• Knowledge of PCIe and/or Ethernet protocols is a plus

How to apply

• Send your resume by email

Location

• Vancouver, Canada, Austin, TX, San Jose, CA