IL
Design Verification Engineer
External job listingat I2INTECH LLC
Tasks Scaling SV/UVM testbenches for compute arrays, DMAs, NoCs & memory subsystems AXI, NoC/crossbar & performance verification Regressions, triage & coverage closure Requirements 8+ yrs...
External source - not verified2 weeks agoOpen until: Jan 10, 2027
Salary
Not provided
Location
San Jose, United States
Employment type
Full time
Workplace
Not provided
Design Verification Engineer
San Jose, United States
Job description
Tasks
- Scaling SV/UVM testbenches for compute arrays, DMAs, NoCs & memory subsystems
- AXI, NoC/crossbar & performance verification
- Regressions, triage & coverage closure
Requirements
- 8+ yrs ASIC design verification
- Make/Perl/Python scripting
- Thrives in a fast-paced, start-up style environment
- BS/MS in EE or CE
- Must be authorized to work in the US
Schedule
- 12 Months
- W2 Only
How to apply
- Send your resume by email
Location
- San Jose, CA