Design Verification Lead Engineer in Redmond, WA
Published on CazVidat Tech do Quest
Lead design verification at Tech do Quest in Redmond, WA. Apply SystemVerilog, UVM, and AMBA expertise in this full-time onsite engineering role.
Salary
$140,000 per year
Location
Redmond, Washington, United States
Employment type
Full time
Workplace
Not provided
Design Verification Lead Engineer in Redmond, WA
$140,000 per year
Job description
Tech do Quest is hiring a full-time Design Verification Lead Engineer for an onsite position in Redmond, Washington. Lead verification for complex designs and help ensure systems meet rigorous quality and performance standards.
Key Responsibilities
- Lead design verification and create and execute project verification plans.
- Develop system-level testbenches using SystemVerilog and UVM to validate design functionality.
- Integrate verification IP (VIP) and develop coverage coding for comprehensive test coverage.
- Use Verilog and VHDL for design modeling and simulation.
- Debug design issues and perform root cause analysis.
- Collaborate with design, validation, and software engineering teams.
- Mentor junior engineers and promote technical excellence and continuous improvement.
Required Qualifications
- Bachelor’s degree in engineering or a related field.
- At least 5 years of experience in design verification or a related role.
- Strong experience with SystemVerilog, UVM, testbenches, and VIP integration.
- Proficiency in Verilog, VHDL, and AMBA protocols.
- Demonstrated debugging and coverage coding skills.
- Ability to lead teams and drive projects to completion.
Compensation and Work Environment
Annual pay is $140,000 per year. This is a full-time, onsite role in Redmond, WA. Tech do Quest offers a collaborative environment that encourages innovation, mentorship, professional development, and career growth.
Frequently asked questions
Is this position remote or on-site?
This role is onsite in Redmond, Washington, so you will need to work from the company's location.
What is the salary for this Design Verification Lead Engineer role?
The salary for this position is USD 140,000 per year.
What kind of experience do I need to qualify for this job?
You should have at least 5 years of experience in design verification or a related role, with strong skills in System Verilog, UVM, testbench development, and VIP integration.
What are the main responsibilities of this role?
You will lead and manage the design verification process, create and execute verification plans, design system-level testbenches, perform debugging, and mentor junior engineers.
What technical skills are required for this position?
Proficiency in System Verilog, UVM, Verilog, VHDL, AMBA protocol standards, debugging, and coverage coding methodologies are required.
Does this company offer opportunities for professional growth?
Yes, Tech do Quest fosters a culture of growth, mentorship, and innovation, with opportunities for professional development and career advancement.