Low Power Design/Methodology Engineer

About the role

Qualcomm is seeking an engineer to design adaptive power management controllers, on-chip sensor controllers and digital power meters. The role supports low-power and power-management IP for wireless SoC chips, and functional safety features in automotive SoC products.

Responsibilities

• Perform RTL design, simulation, synthesis, timing analysis, lint checks, clock domain crossing checks, conformal low-power checks and formal verification for IP blocks.
• Work with technology and circuit design teams to close IP block specifications and requirements.
• Work with verification and physical design teams to complete IP design implementation.
• Support SoC integration of low-power and power-management IP solutions into wireless SoC chips and front-end design flows.
• Work with system, software and test teams to enable low-power features in wireless SoC products and functional safety features in automotive SoC products.
• Create and enhance low-power methodologies across the design cycle from RTL to GDS, assess their effects on design and verification phases, and address issues.
• Provide feedback on low-power chip and system architecture.
• Perform block- and chip-level power analysis and create block-level power models.

Requirements

• Three years of experience in low-power digital ASIC design.
• Familiarity with ASIC front-end design processes and flows, including u-arch, RTL coding, simulation, synthesis and STA.
• Familiarity with scripting languages such as Python, Perl and TCL.
• Understanding of electrical engineering concepts, circuit analysis and logic design.
• Previous AVS (adaptive voltage scaling) experience is desired.
• Familiarity with advanced low-power techniques and tools such as UPF, CLP, power-aware DV and high-speed clocking is desired.
• Proficiency in Verilog/System Verilog coding, verification techniques and scripting languages such as Perl, Python, Tcl and Make is preferred.

Key facts

• Requires three years of experience in low-power digital ASIC design.
• The role includes RTL design, simulation, synthesis, timing analysis and formal verification for IP blocks.
• Familiarity with ASIC front-end design processes and flows is required.