Physical Design Engineer

Tasks

• Own full-chip top-level floorplanning, including die/partition planning, macro and memory placement, and pin/port alignment.
• Define partition abutment, repeating structures, channels, and feedthrough strategies for seamless block integration.
• Drive top-level PPA optimization (Power, Performance, and Area) across the chip hierarchy.
• Plan and review top-level power grids and Power Delivery Networks (PDN) in coordination with EM/IR sign-off.
• Develop and maintain top-level SDC constraints and timing budgets, distributing partition constraints to block owners.
• Collaborate with ASIC vendors, IP partners, and block-level physical design teams on floorplanning, partitioning, and Static Timing Analysis (STA) reviews.

Requirements

• Cadence Innovus
• Synopsys Fusion
• Full-chip / top-level physical design
• Floorplanning, partitioning, and macro placement
• PPA optimization and timing constraints
• Power grid / PDN planning and EM/IR sign-off
• SDC development and STA coordination

Schedule

• Contract

How to apply

• Share your updated resume by email.

Location

• Austin, TX / San Jose, CA (Onsite)