Physical Design Engineer

Tasks

• Perform synthesis and optimize timing-critical designs.
• Develop and refine floorplans using Innovus.
• Identify timing bottlenecks and improve PPA.
• Collaborate with RTL and external P&R teams to achieve timing closure.

Requirements

• 10+ Years
• Cadence Genus – Logic Synthesis
• Cadence Innovus – Physical Design & Floorplanning
• PPA Optimization (Power, Performance & Area)
• Timing Closure & Timing Analysis
• RTL-to-Implementation Correlation
• Advanced Technology Nodes – N5 / N3 or below
• Large-Scale SoC / AI Chip Design Experience
• Collaboration with RTL, Architecture & P&R Teams

Schedule

• Contract

How to apply

• Share your updated resume via DM.

Location

• San Jose, CA