Senior RTL/STA Engineer

🚀 We Are Hiring: Senior RTL / STA Engineer (San Jose, CA)
Are you a senior RTL / Static Timing Analysis (STA) Engineer (6–8+ years) with deep hands-on expertise in timing constraint development, timing closure, Synopsys PrimeTime, and RTL design?
We are seeking a seasoned semiconductor professional.
📌 Role Highlights
Location: San Jose, California (On-site preferred)
🔑 Key Responsibilities
Timing Constraints & Closure: Develop, review, debug, and verify complex timing constraints (SDC) across functional, test, and DFT operating modes.
RTL Design & Collaboration: Contribute to RTL design and partner closely with verification, synthesis, and DFT teams to resolve architectural and implementation bottlenecks.
STA & Synthesis Analysis: Analyze timing behavior, debug reports using industry-standard tools (Synopsys PrimeTime, Fusion Compiler), and drive timing closure.
Automation & Scripting: Leverage scripting languages (Python, Tcl, Perl) to enhance constraint checks, analysis, and engineering productivity workflows.
💻 Profile & Qualifications
Education & Experience: Bachelor’s with 8+ years, Master’s with 6+ years, or PhD with 3+ years of relevant ASIC/STA experience.
Core Technical Stack: Hands-on experience with RTL design, SDC constraint development, and timing closure methodologies.
Scripting Proficiency: Strong programming skills in at least two: Python, Tcl, Perl, or Makefile.
Preferred Experience: Synopsys PrimeTime, Fusion Compiler, Design Compiler, PCIe/TSMC memory timing, CDC/RDC, Conformal verification, and Tessent DFT.
📥 How to Apply
If you are an RTL/STA expert ready for a high-impact ASIC engagement, let's connect!
👉 Drop your resume, and current location in the comments or send a direct DM to schedule an immediate review!
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