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Sr Staff/Principal RTL Design Engineer
External job listingat Skalensemi
Requirements 5+ Years RTL Design | Verilog | SystemVerilog | ASIC | SoC | VCS | Xcelium | Questa | Python | C/C++ | Synthesis | Genus | Design Compiler | STA | SDC | CDC | AMBA AXI/AHB/AP...
External source - not verified6 days agoOpen until: Feb 1, 2027
Salary
Not provided
Location
San Jose, United States
Employment type
Full time
Workplace
Not provided
Sr Staff/Principal RTL Design Engineer
San Jose, United States
Job description
Requirements
- 5+ Years
- RTL Design | Verilog | SystemVerilog | ASIC | SoC | VCS | Xcelium | Questa | Python | C/C++ | Synthesis | Genus | Design Compiler | STA | SDC | CDC | AMBA AXI/AHB/APB | DFT | Scan | BIST | ATPG | Silicon Bring-Up | SerDes | FPGA
- Timing Analysis | LEF/Lib | Cadence Virtuoso | High-Speed SerDes | Electro-Optical Systems | Photonics (Good to Have)
- U.S. work authorization required without current or future visa sponsorship.
Schedule
- Fully Onsite
- Full-Time Direct Client
How to apply
- Apply by email.
Location
- San Jose, CA