Sr Staff/Principal RTL Design Engineer

🚀 WE ARE HIRING | Sr Staff / Principal RTL Design Engineer
📍 San Jose, CA | 🏢 Fully Onsite
🏭 Client: Mid-Sized Product Startup
💼 Full-Time Direct Client | 🎯 5+ Years
🔹 Key Skills: RTL Design | Verilog | SystemVerilog | ASIC | SoC | VCS | Xcelium | Questa | Python | C/C++ | Synthesis | Genus | Design Compiler | STA | SDC | CDC | AMBA AXI/AHB/APB | DFT | Scan | BIST | ATPG | Silicon Bring-Up | SerDes | FPGA
⭐ Good to Have: Timing Analysis | LEF/Lib | Cadence Virtuoso | High-Speed SerDes | Electro-Optical Systems | Photonics
USA Work Authorization: U.S. work authorization required without current or future visa sponsorship.
📩 Apply: 👉 Please share with your network!
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