STA Engineer

Tasks

• Develop and validate timing constraints for intricate SoC designs.
• Perform static timing analysis (STA) using industry-standard tools (e.g., PrimeTime, Tempus).
• Define and implement timing signoff methodologies, including process corners, derates, and uncertainties.
• Conduct pre-route timing checks and quality of results (QoR) analysis.
• Automate timing analysis processes using scripting languages such as Tcl or Perl.
• Provide guidance on clock tree synthesis and optimization for energy-efficient designs.
• Ensure compliance with timing signoff checklists and criteria.

Requirements

• Experience with high-complexity silicon in advanced technology nodes.
• Familiarity with timing constraint development for hierarchical designs.
• Knowledge of clock tree planning and implementation for SoCs.
• Experience with timing ECO creation and final timing signoff.
• Proficiency in using STA tools (e.g., PrimeTime, TCM, Tempus) and scripting languages (e.g., Tcl, Perl).
• Proficiency in using synthesis tools (Genus)
• Strong understanding of ASIC design flows, including RTL and place-and-route.
• Excellent problem-solving skills and attention to detail.
• Effective communication and teamwork abilities.
• Bachelors and 8+ years of related experience; at this level post-graduate coursework may be desirable or Masters degree and 6+ years of related experience or PhD and 3+ years of related experience.

Schedule

• Full Time

How to apply

• Send your updated resume.

Location

• San Jose, CA