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ASIC Engineer
External job listingat Confidential
Requirements Mid to Senior / Principal (Level 4 & 5) SystemVerilog, Verilog, UVM, RTL Implementation and Timing Closure. High-speed Interface IPs (SerDes, LPDDR, MIPI, UFS) or Mixed-Signa...
External source - not verified9 hours agoOpen until: Jan 28, 2027
Salary
Not provided
Location
Austin, United States
Employment type
Full time
Workplace
Not provided
ASIC Engineer
Austin, United States
Job description
Requirements
- Mid to Senior / Principal (Level 4 & 5)
- SystemVerilog, Verilog, UVM, RTL Implementation and Timing Closure.
- High-speed Interface IPs (SerDes, LPDDR, MIPI, UFS) or Mixed-Signal Behavioral Modeling.
Schedule
- 12+ month contracts
- On-site / Hybrid options available.
How to apply
- Send your updated resume directly by email.
- Or drop a direct message on LinkedIn.
Location
- Santa Clara / San Jose, CA
- Austin / Dallas, TX