Design Verification Engineer

We're working with a well-funded, highly selective AI infrastructure startup building silicon for large-scale AI inference and training. Founded by veteran chip architects who previously led a major AI hardware program at a top tech company, the business has grown fast and is backed by top-tier investors.
They're looking for verification engineers to help build best-in-class silicon for high-performance, sustainable GenAI, across compute, memory management, and high-speed connectivity. They have openings at all levels.
Scope isn't fixed here: they want versatile engineers who can move between core verification and tooling rather than staying in one lane.
ResponsibilitiesShape the verification methodology, building a scalable approach across block, subsystem, full-chip and system-level validationOwn verification execution at subsystem and chip level, building the testbenches, tests and artifacts needed to close structural and functional coveragePlan and drive verification reviews (test plans, execution progress, closure), both intermediate and sign-off, towards milestones including design freeze and tapeoutWork from architecture and design specifications through to production silicon
RequirementsConcept-to-silicon experience: you've driven verification from an architecture or design spec through to production siliconWorking knowledge of SystemVerilog, Python and C/C++ for verification and silicon modellingProduction experience with UVM and assertion-based verification, and comfort with both formal and simulation-based verificationProduction experience building portable tests and drivers that carry over into silicon validation and post-silicon debugStrong grasp of micro-architecture and design concepts in high-performance compute (CPUs, GPUs, accelerators), high-speed connectivity and memory management
Nice to HaveFamiliarity with emulation and prototyping platforms and methodologiesHands-on participation in silicon debug and bring-up
What Sets This Role ApartReal mission: an AI silicon company building best-in-class, power-efficient chips for GenAI, spanning compute, memory management and high-speed connectivityScope from block to system: you're not confined to one level of the stack, and you'll see verification through to tapeoutOwnership: you take real responsibility for subsystem and chip-level verification, and help define the methodology
Package & ProcessCompensation is highly competitive, with strong equity and full benefits.