Design Verification Engineer, Hardware

About the role

River AI is building personal AI owned and shaped by each individual, rewriting the stack from scratch across personal hardware for local inference, bespoke training infrastructure, next-generation UIs, and frontier deep learning research.

River AI seeks design verification engineers to ensure its high-performance custom silicon is functionally correct. Starting from architectural and micro-architectural definitions, you will define test bench boundaries and implement test environments across verification methodologies, including simulation, formal, and emulation. You will collaborate with RTL design, performance modeling and verification, and compiler teams.

Responsibilities

• Define comprehensive verification plans by extracting features from architectural and micro-architectural specifications for complex blocks.
• Architect and implement scalable, reusable, robust test benches using SystemVerilog and UVM (Universal Verification Methodology).
• Develop constrained-random sequences and test cases to achieve high functional coverage, including architectural corner cases and error conditions.
• Define and implement functional coverage models and analyze code coverage to quantify verification progress.
• Use formal methods, including SVA and Property Checking, where applicable to prove critical logic.
• Use emulation and prototyping platforms such as ZeBu/HAPS and Palladium/Protium for scaled testing.
• Debug failures.

Key facts

• The role focuses on functional verification of high-performance custom silicon.
• The work includes SystemVerilog, UVM, constrained-random testing, coverage, formal verification, and emulation.
• The role collaborates with RTL design, performance modeling and verification, and compiler teams.