Physical Design Manager ( Fusion Compiler )

Title :: Physical Design Technical Manager ( Fusion Compiler )Location :: Santa Clara, CA

Work Experience
What You will DoDrive physical design flow: synthesis, floorplanning, placement, CTS, routing, timing closureDeliver low power designs using advanced UPF methodologies on 5nm/3nm nodesResolve SoC/SS integration challenges including SDC constraints and UPF promotion/pushdownDevelop and maintain automation flows using Tcl, Python, and ShellCollaborate with cross-functional teams for design closure and signoffMentor and lead junior team membersInnovate and contribute to flow/methodology improvements
What You Will Bring:Experience in physical design and timing closureBachelors degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experienceKnowledge of RTL2GDSII flow and design tape-outs in 5nm or below process technologiesExperience with EDA tools like DC/Genus, Innovus/ICC2, Primetime, Fusion Compiler, Redhawk/Voltus, or CalibreHands-on experience in SoC floor planning, place & route, power and clock distribution, and timing convergence of high-frequency designsKnowledge of geometry/process/device technology implications on physical design10+ years of experience in interpersonal, teamwork, and demonstrated experience communicating and interfacing with cross-functional teams, IP, and EDA vendorsProgramming/scripting skills: TCL, Python, Perl or Shell