Sr. Physical Design Engineer

Tasks

• Execute end-to-end Physical Design, Synthesis, Physical Verification, and Timing Closure activities.
• Setup and synthesize RTL designs.
• Perform timing closure using various methodologies and strategies, including top-level STA.
• Conduct EM/IR analysis.
• Execute Place & Route (P&R).
• Develop and optimize Clock Tree Synthesis (CTS), including custom clock trees, insertion delay reduction, and skew balancing.
• Perform floorplanning and layout activities, preferably with top-level floorplanning expertise.
• Contribute to flow and methodology development.
• Collaborate closely with IC Design and RTL Engineering teams.

Requirements

• Strong experience with Cadence Innovus.
• Expertise in the complete Physical Design cycle from RTL to Tape-out.
• Hands-on experience in: Synthesis, Static Timing Analysis (STA), Timing Closure, Place & Route, Clock Tree Synthesis (CTS), Floorplanning, Physical Verification, EM/IR Analysis
• Strong TCL and/or PERL scripting skills.
• Proficiency with industry-standard EDA tools.
• Excellent communication and collaboration skills.
• Bachelor's degree in electrical engineering, Electronics Engineering, or related field.
• Preferred: Deep expertise in top-level floorplanning and STA.
• Preferred: Proven success delivering complex ASIC/SoC designs through tape-out.

Schedule

• Onsite

How to apply

• Send your updated resume by email.

Location

• San Jose, CA
• San Diego, CA
• Irvine, CA