Sr. Principal Front-End Design Automation Engineer
External job listingat Ampere
Ampere seeks a Sr. Principal Front-End Design Automation Engineer to advance EDA tooling, RTL design, verification, and AI-enabled automation.
Salary
Not provided
Location
Portland, United States
Employment type
Full time
Workplace
Not provided
Sr. Principal Front-End Design Automation Engineer
Portland, United States
Job description
About the role
Ampere is a semiconductor design company focused on high-performance, energy-efficient AI compute. As a pioneer in energy-efficient high-performance computing, Ampere is part of the Softbank Group of companies driving sustainable computing for AI, Cloud, and edge applications.
As a Sr. Principal Front-End Design Automation (EDA/DevOps) Engineer, you will partner strategically with Ampere’s RTL and Verification organizations to improve pre-silicon productivity through scalable automation, systems, and platform capabilities. You will lead cross-functional initiatives across hardware, software, and IT, and provide expert guidance on EDA tooling and Ampere flows.
Responsibilities
- Provide technical guidance for EDA tools and Ampere design and verification flows, establishing standards and mechanisms to improve productivity and reliability.
- Collaborate with RTL design and verification teams to define and deploy improved methods of work.
- Architect, document, deploy, and administer custom Ampere automation and services that streamline RTL design and verification and reduce cycle time and operational overhead.
- Enable and support EDA tools used for RTL design and verification, including SystemVerilog simulation, Lint, CDC, RDC, UPF, and debug.
- Partner with IT, EDA vendors, RTL design, and verification teams to deliver high-performance, efficient solutions.
- Drive AI-enabled automation for design and verification.
- Automate end-to-end workflows across on-prem and cloud, and scale infrastructure to improve design quality and expand AI impact in verification and design.
How to apply
Apply directly on CazVid.
Key facts
- The role partners with Ampere’s RTL and Verification organizations to improve pre-silicon productivity.
- The work includes EDA tools for RTL design and verification, such as SystemVerilog simulation, Lint, CDC, RDC, UPF, and debug.
- The role drives AI-enabled automation for design and verification.
Frequently asked questions
What does this role involve?
It involves leading automation, systems, and platform capabilities to improve pre-silicon productivity. The role partners with RTL and Verification organizations.
Which EDA tools does the role support?
The role enables and supports tools for RTL design and verification, including SystemVerilog simulation, Lint, CDC, RDC, UPF, and debug.
How can I apply?
Apply directly on CazVid.