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SDC/Design Engineer
External job listingat Iis
About the role We are looking for an experienced SDC / Design Engineer with strong expertise in ASIC design, timing constraints, and Static Timing Analysis (STA). Requirements 8+ Years Bl...
External source - not verified15 hours agoOpen until: Feb 3, 2027
Salary
Not provided
Location
San Jose, United States
Employment type
Full time
Workplace
Not provided
SDC/Design Engineer
San Jose, United States
Job description
About the role
We are looking for an experienced SDC / Design Engineer with strong expertise in ASIC design, timing constraints, and Static Timing Analysis (STA).
Requirements
- 8+ Years
- Block-Level and Full-Chip SDC Development
- Static Timing Analysis (STA)
- Synopsys PrimeTime / Cadence Tempus
- Verilog / SystemVerilog
- Synopsys Design Compiler (DC/DCG/FC)
- Clocking Constraints and Timing Exceptions
- TCL / Python / Perl Scripting
- Preferred: Synopsys TCM / Cadence CCD
- Preferred: SpyGlass CDC and Glitch Analysis
- Preferred: Formal Verification (Formality / LEC)
Schedule
- Day-1 Onsite
- 1099 / C2C
How to apply
- Send your resume or contact me directly.
Location
- San Jose, CA