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SDC/STA Design Engineer
External job listingat I2INTECH LLC
About the role Help build next-generation networking chips by owning full-chip timing constraints, from block level to tape-out! Tasks Own full-chip SDCs and close timing across multiple...
External source - not verified8 days agoOpen until: Jan 15, 2027
Salary
Not provided
Location
San Jose, United States
Employment type
Full time
Workplace
Not provided
SDC/STA Design Engineer
San Jose, United States
Job description
About the role
Help build next-generation networking chips by owning full-chip timing constraints, from block level to tape-out!
Tasks
- Own full-chip SDCs and close timing across multiple modes with PD & DFT teams
- Build methodology to promote block SDCs to full-chip (and back)
- Ensure SDC quality and correctness early in the design cycle
- Review block SDCs & clocking diagrams, and mentor RTL owners
- Create full-chip clocking diagrams and documentation
- Optional: block-level RTL design or IP integration
Requirements
- 8+ yrs ASIC experience
- Block/full-chip SDC in functional & test modes
- Clock groups, exceptions & clock exclusivity
- STA with PrimeTime or Tempus
- Synthesis (DC/DCG/Fusion Compiler) & Verilog/SV
- Python/Perl/Tcl scripting
- Bonus: TCM, Conformal Constraint Designer, Spyglass CDC, Formality/LEC
- Must be authorized to work in the US
Schedule
- Day-1 Onsite
- 12 Months
- W2 Only
How to apply
- Send your resume by email
Location
- San Jose, CA